1. Field of the Invention
The present invention relates generally to integrated circuit memory devices, and more particularly to a memory device having multiple redundant columns with offset segmentation boundaries.
2. Description of the Related Art
Memory tests on semiconductor devices, such as random access memory (RAM) integrated circuits, e.g., DRAMs, SRAMs and the like, are typically performed by the manufacturer during production and fabrication to locate defects and failures in such devices that can occur during the manufacturing process of the semiconductor devices. Defects may be caused by a number of factors, including particle defects such as broken or shorted out columns and rows, particle contamination, or bit defects. The testing is typically performed by a memory controller or processor (or a designated processor in a multi-processor machine) which runs a testing program, often before a die containing the semiconductor device is packaged into a chip.
Random access memories are usually subjected to data retention tests and/or data march tests. In data retention tests, every cell of the memory is written and checked after a pre-specified interval to determine if leakage current has occurred that has affected the stored logic state. In a march test, a sequence of read and/or write operations is applied to each cell, either in increasing or decreasing address order. Such testing ensures that hidden defects will not be first discovered during operational use, thereby rendering end-products unreliable. In order to reduce the number of address lines and time required to conduct a memory test, the memory tests may be done in a compressed mode in which multiple banks of memory locations are tested in parallel rather than one at a time.
Many semiconductor devices, particularly memory devices, include redundant circuitry on the semiconductor device that can be employed to replace malfunctioning circuits found during testing. During the initial testing of a memory device, defective elements are repaired by replacing them with non-defective elements referred to as redundant elements. By enabling such redundant circuitry, the device need not be discarded even if it fails a particular test. FIG. 1 illustrates one memory bank 11 of a memory array 10 of a conventional memory device. Memory bank 11 includes a plurality of memory cells arranged in rows and columns. The architecture of memory bank 11 illustrated in FIG. 1 divides the rows into eight row blocks, numbered row block &lt;0&gt; to row block &lt;7&gt;. It should be understood that the eight row blocks illustrated in FIG. 1 are exemplary only, and a memory device is not limited to eight row blocks. It should also be understood that FIG. 1 illustrates only a portion of array 10 of a memory device. Array 10 may be provided with a plurality of memory banks. Additionally, a mirror image memory bank of the memory bank 11 typically provided located to the right of column decoder 18 and redundant column decoder 20.
A memory cell is accessed by applying a specific row address Qn row address lines 12 to the row decoders 14a-14h and a column address on column address lines 16 to column decoder 18 and redundant column decoder 20. Row decoders 14a-14h will activate the selected cell row via one of the row lines 13, while column decoder 18 and redundant column decoder 20 will activate the selected cell column via one of the column lines 19.
A redundant column 22 spans tie eight row blocks &lt;0&gt; to &lt;7&gt;. Memory devices typically employ redundant rows and columns of memory cells so that if a memory cell in a column or row of the primary memory array is defective, then an entire column or row of redundant memory cells can be substituted therefore. It should be noted that while only one redundant column is depicted, a typical modern high density memory device may have more than one redundant column and may also be provided with redundant rows as well. Substitution of one or more of the spare rows or columns is conventionally accomplished by opening a specific combination of fuses (not shown) or closing antifuses in one of several fuse banks (not shown) on the die. A selected combination of fuses are blown to provide an address equal to the address of the defective cell. For example, if the defective cell has an eight-bit binary address of 11011011, then the third and sixth fuses in a set of eight fuses within one of several fuse banks will be blown, thereby storing this address. A compare circuit (not shown) compares each incoming address to the blown fuse addresses stored in the fuse banks to determine whether the incoming address matches with one of the blown fuse addresses. If the compare circuit determines a match, then it outputs a match signal (typically one bit). In response thereto, the column decoder 18 is disabled and the redundant column decoder 20 is activated to access the redundant column 22. A plurality of sense amplifiers 24 are provided adjacent to each row block to read the data from a selected cell and output it to one of the data lines 15.
The columns of redundant memory cells necessarily occupy space on the die. Therefore, it is desirable to obtain the maximum number of repairs using a minimum number of spare columns. One conventional way to increase the effectiveness of a redundant column is to segment the redundant column. By segmenting the redundant columns, a defective memory cell in a region of the primary memory array can be repaired with only a portion of the redundant column. For example, the redundant column 22 can be segmented into four regions, Segment &lt;0&gt; to Segment &lt;3&gt;, as illustrated in FIG. 2. A fuse bank (not shown) is associated with each bank to store the column address. Only one of the four segments will be selected to compare the applied address with the address stored in the selected redundant column fuse bank. The column segment selected is determined by which row block, i.e., row block &lt;0&gt; to &lt;7&gt; is enabled by one of row decoders 14a-14h. Typically, the most significant bits (MSBs) of the row address are used to select one of the four segments for the comparison, i.e., MSBs 00 would select Segment &lt;0&gt;, MSBs 01 would select Segment &lt;1&gt;, MSBs 10 would select Segment &lt;2&gt;, and MSBs 11 would select Segment &lt;3&gt;.
By segmenting the redundant column, a defective memory cell in the primary memory array can be repaired with only a portion of the redundant column, i.e., only one segment of the redundant column. Thus, a second defective memory cell can be repaired using a second segment of the redundant column, a third defective memory cell can be repaired using a third segment of the redundant column, and a fourth defective memory cell can be repaired using a fourth segment of the redundant column. This technique allows for a greater number of single bit errors to be repaired utilizing only a single physical redundant column, instead of having to utilize an entire column for each defective cell. Thus, the area on the die required for redundant columns can be significantly reduced.
Another advantage of segmenting the columns is that address compression test modes can be implemented such that compressed addresses do not cross redundancy planes. For example, four redundant column circuits might each have a single fuse bank. A memory array is connected to each of the four redundant column circuits. Only one of the circuits will be active at a time based on which row block is enabled. If the selected redundant column circuit detects a column address match, the redundant column is turned on in all four of the memory arrays. In this manner, each of the four redundant column circuits controls one segment of the physical redundant column in all four memory arrays. In address compression test mode, address bits which are used to select one of the four memory arrays can be compressed out, i.e., made "don't cares." All four memories can be accessed together, the data logically combined, and read out on a single input/output pin. If a defective cell is detected, a redundant column may be used to repair the device without regard for which of the memory arrays actually contains the defective memory cell, since all four arrays are repaired by the redundant column. By utilizing the address compression test mode, the time required for the testing can be reduced, thus increasing throughput.
There are drawbacks, however, with the segmentation approach described above. Although the segmentation of the redundant column allows for multiple repairs using a single column, under certain conditions the segmented column may not be used as efficiently as possible and memory cells which are not defective may be unnecessarily repaired. For example, some circuit defects can effect the digit lines of an adjacent row block that shares a sense amplifier with the defective circuit and thereby cause failures in the adjacent row block. This is due to the isolation and equilibrate devices, as are known in the art for memory devices, which are turned on when the array is inactive. FIG. 3 illustrates in greater detail the portion 30 designated by the dashed lines of memory bank 11 illustrated in FIG. 1. The digit lines 32, 34 of a memory device are typically designed to equilibrate to a particular reference voltage when the array is idle. When the isolation lines 36 are on, transistors 38, 38a, 40 and 40a are switched on, causing the digit lines from adjacent row blocks to be electrically connected through sense amplifier 24, i.e., digit lines 32 and 32a are connected and digit lines 34 and 34a are connected.
If a memory defect causes the digit lines to achieve an incorrect equilibrated potential, then the sense amplifier may not be able to detect the data stored in a selected memory cell during a read cycle. For example, a defect in memory cell 42 of row block &lt;3&gt; could cause digit line 32 to equilibrate to a ground potential rather than the required reference potential. Since digit line 32 shares sense amplifier 24 with digit line 32a in row block &lt;4&gt;, digit line 32a may also equilibrate to a ground potential. If this occurs, then two redundant column segments will need to be programmed to repair the device. The first redundant column segment, i.e., Segment &lt;1&gt; of FIG. 2, will replace segments of the column for row blocks &lt;2&gt; and &lt;3&gt;, and a second column segment, i.e., Segment &lt;2&gt; of FIG. 2, will replace segments of the column for row blocks &lt;4&gt; and &lt;5&gt;. Thus, row blocks &lt;3&gt; and &lt;4&gt; will be repaired. However, two fuse banks have been used, one for each redundant column segment, and row blocks &lt;2&gt; and &lt;5&gt; have been repaired unnecessarily, reducing the efficiency of the redundant column.
Thus, there exists a need for a segmented column architecture that provides the benefits of increased single bit repair, address compression compatibility, and single bank repair across any two row blocks.